The present invention relates to a method of manufacturing a semiconductor device.
As the related art which is the background of the present invention, Japanese Patent Application Publication No. 2003-318398 filed by the applicant of the present invention has been disclosed. In this related art, an N− type polycrystalline silicon region and an N+ type polycrystalline silicon region are formed so as to adjoin each other on one main surface of a semiconductor body in which an N− type silicon carbide epitaxial region is formed on an N+ type silicon carbide substrate, in addition, the epitaxial region, the N− type polycrystalline silicon region and the N+ type polycrystalline silicon region forms a hetero junction. Furthermore, a gate electrode is formed so as to be adjacent to a junction portion between the epitaxial layer, and the N+ type polycrystalline silicon region while interposing a gate insulating film therebetween. The N− type polycrystalline silicon region is connected to a source electrode, and a drain electrode is formed on a backside surface of the N+ type silicon carbide substrate.
The semiconductor device of the related art having the structure as described above functions as a switching device by controlling an electric potential of the gate electrode in a state where the source electrode is grounded and a predetermined positive electric potential is applied to the drain electrode. That is, in the state where the gate electrode is grounded, reverse bias is applied to the hetero junction formed of the N− type polycrystalline silicon region, the N+ type polycrystalline silicon region and the epitaxial region so that no current flows between the drain electrode and the source electrode. However, in the state where the predetermined positive voltage is applied to the gate electrode, gate electric filed acts on a hetero junction interface between the N+ type polycrystalline silicon region and the epitaxial region, and an energy barrier formed by the hetero junction surface on a gate oxide film interface is made to be thin. Therefore, current flows between the drain electrode and the source electrode. In this related art, since the hetero junction portion is used as a control channel for cutting-off and flowing of the current, the device functions with a channel length having a thickness equal to that of the hetero barrier. Therefore, a conduction characteristic of low resistance can be obtained.